• base integer ISA + optional extensions Family | # of registers ------ | -------------- RV32I | 32 RV32E | 16 RV64I | 32 RV128I | 32 RV = RISC-V width of registers (address space size) = 32, 64, 128 number of registers for example 16 is embedded
• RV32I, RV64I
  • 32 registers: x0, x1, …, x31
  • x0 is always zero
• Byte Addressable Memory
• RV64I (double word)

Moving data from Memory to register.

RISC-V Instructions

Example: d = b + c - e x3 x6 x2 x4 Regisyters since the processor can only execute one computation at a time: t = b + c (1) x5 register d = t - e (2) assembly instructions: add x5, x6, x2 (1) sub x3, x5, x4 (2) gives machine code for RISC-V RV64I

R[x5] = R[x6] + R[x2]