Reduced Instruction Set Computer (RISC)
Terminology:
- coprocessor
- unit attached to RISC-V cre which is mostly sequenced by RISC-V instruciton stream but has additional state and instruction set extensions
- accelerator
- non-programmable
- e.g. I/O accelerators which offload I/O tasks from main application cores.
- software running on RISC-V can run at a privilege level encoded as a mode
- M-mode: machine code (highest privilege)
- U-mode: user mode
- S-mode: supervisor mode
- user and supervisor mode are for conventional applicaiton and OS usage respectively
RISC-V ISA (Instruction Set Architecture)
Instructions are 32-bits.