Design Ideas

• abstraction - levels of design Transistor, gatearchitecture behavior (Data Flow Graph)
• parallelism to improve performance
• common fast - optimize code in assembly
• prediction:
• memory hierarchy: small memory is faster, put it closer to processor.
• testable/reliable

Bellow Your Program

• Application software
• System Software
  • Compiler
  • Operating System: service code
  • Hardware

Levels of Program Code

• High-leve language
• Assembly
• Hardware representation
• O/S loads the program
• O/S starts the execution of the program: creates a “Process” (when it’s born)

Components of a Computer

• Same components for all kinds of computer
  • Desktop, server, embedded
• Input/output includes
  • Use-interface devices
    • Display, keyboard, mouse
  • Storage devides
    • Hard disk, CD/DVD, flash
  • Network adapters
    • For communicating with other computers

Performance

”X is n time faster than Y”

Performance${}_x$ / Performance${}_y$ = Execution time${}_y$ / Execution time${}_x$ = n

Make sure to put the smaller execution time in the denominator when comparing the performance of two processors.

• Amdahl’s Law

  Execution time after improvement = [execution time affected by improvment / amount of improvment] + execution time unaffected

• CPU execution time

  • cpu time does NOT inlcude time waiting for I/O or in OS waiting for tasks to be performed by CPU
  • clock frequency in kHz or MHz
  • CPI
  • MIPS

CPU execution time

= (# of clock cycles) (clock period) = (# of clock cycles) / (clock frequency) = [instruction] x [CPI] / [clock frequency]

MIPS = [clock rate] / [CPI 10${}^6$]

• Power
• RISC
  • different from : CISC = comlplex instruction set computer
• RISC-V core terminology:
  • coprocessor
  • accelerator
  • software running on RISC-V can run at a privilege level encoded as a mode
  • user and supervisor mode are for vconventional applicaiton and OS usage respectively

Exam question:

RISC stands for reduced instruction set computer : high performance Smaller memory is not slower. Piplining improves throughput Know a typical piplining example and parallelism example. RAM: random access memory SRAM: static, all data is gone, volatile, 6 of more transistor per bit dRAM: dynamic, also volatilve, 1 transistor per bit How many transistor for a register? 2 Cache is a small amount of memory.

What is on the Processor architecture known as Datapath: - SRAM - Flash: non-volatile, when pulling the plug out, the program is still there - OTP: One time programmable, “antifuse”

Main Memory Chip: - DRAM: contains more memory

HDD: - Secondary memory - non volatile because it is magnetic