2. Intrusction Set Architecture (ISA)

ISA RISC-V instructions are in 32 bits. RISC-V ISA

In this course we are going to use RV32I and RV64I.

RV64I: 64 stands for the width of Registers RV32I: 32 width of Registers Both has 32 bit instruction

RISC-V assembly language notation (registers): - x0 is always zero. - load from memory from register to perform computation - use registers because faster they are closer to the processor - RV64I - byte addressable memory - 2^61 double words in memory - e.g. 2^64/2^3 bytes/double word = 2^61 double words ‘Little endian’ lsbyte stored at address of word - pointing at byte 0 of the address 0 - increment by 4 to get the next word in memory because it’s byte addressable memory. B = bytes - memory contains 2^61 memory words - RV32I 2^32 bytes addressable 2^31 half words addressable